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document no. e0300e90 (ver. 9.0) date published november 2004 (k) japan url: http://www.elpida.com ? elpida memory, inc. 2002-2004 preliminary data sheet 256m bits ddr mobile ram ? edk2516cbbh (16m words 16 bits) description the edk2516cbbh is a 256m bits ddr mobile ram organized as 4,194,304 words 16 bits 4 banks. the ddr mobile ram achieved low power consumption and high-speed data transfer using the 2 bits prefetch- pipeline architecture. command and address inputs are synchronized with the positive edge of the clock. data inputs and outputs are synchronized with both edges of dqs (data strobe). dll is not implemented. this product is packaged in 60-ball fbga. features ? low voltage power supply ? vdd: 1.8v 0.15v ? vddq: 1.8v 0.15v ? wide temperature range ( ? 25 c to +85 c) ? programmable partial array self refresh ? programmable driver strength ? auto temperature compensated self refresh by built-in temperature sensor. ? deep power down mode ? small package (60-ball fbga) ? fbga package with lead free solder (sn-ag-cu) ? data rate: 200mbps/io(max) ? double data rate architecture: two data transfers per one clock cycle ? bi-directional, data strobe (dqs) is transmitted /received with data, to be used in capturing data at the receiver. ? 1.8v lvcmos interface ? command and address signals refer to a positive clock edge ? quad internal banks controlled by ba0 and ba1 ? data mask (dm) for write data ? wrap sequence = sequential/ interleave ? programmable burst length (bl) = 2, 4, 8 ? automatic precharge and controlled precharge ? auto refresh and self refresh ? 8,192 refresh cycles/64ms (7.8 s maximum average periodic refresh interval) ? burst termination by burst stop command and precharge command pin configurations /xxx indicates active low signal. a b c d e f g h j 123 789 (top view) k vss dq15 vssq vddq dq0 vdd dq14 dq13 vddq vssq dq2 dq1 dq12 dq11 vssq vddq dq4 dq3 dq10 dq9 vddq vssq dq6 dq5 dq8 vssq vddq ldqs dq7 udqs nc udm vdd ldm nc vss ck cke /cas /ras /we ck a12 a11 a9 ba0 ba1 /cs a8 a7 a6 a0 a1 a10 vss a5 a4 a3 a2 vdd a0 to a12 ba0, ba1 dq0 to dq15 udqs, ldqs /cs /ras /cas /we udm, ldm ck /ck cke vdd vss vddq vssq nc address input bank select address data-input/output input and output data strobe chip select row address strobe command column address strobe command write enable write data mask clock input differential clock input clock enable power for internal circuit ground for internal circuit power for dq circuit ground for dq circuit no connection 60-ball fbga /
edk2516cbbh preliminary data sheet e0300e90 (ver. 9.0) 2 ordering information part number organization (words bits) internal banks clock frequency mhz (max.) /cas latency package EDK2516CBBH-10-E 16m 16 4 100 3 60-ball fbga part number elpida memory density / bank 25: 256m /4-bank bit organization 16: x16 voltage, interface c: vdd = 1.8v, vddq = 1.8v, lvcmos die rev. package bh: fbga (board type) speed 10: 100mhz/cl3 (200mbps) product code k: ddr mobile ram type d: monolithic device e d k 25 16 c b bh - 10 - e environment code e: lead free
edk2516cbbh preliminary data sheet e0300e90 (ver. 9.0) 3 contents description.................................................................................................................... .................................1 features....................................................................................................................... ..................................1 pin config urations ............................................................................................................. ............................1 ordering in format ion........................................................................................................... ...........................2 electrical sp ecifications...................................................................................................... ...........................4 block diagram .................................................................................................................. ...........................10 pin function................................................................................................................... ..............................11 command oper ation .............................................................................................................. .....................13 simplified st ate di agram ....................................................................................................... ......................20 operation of the ddr mobile ram ................................................................................................ .............21 initializ ation ................................................................................................................. .................................21 timing wave forms............................................................................................................... ........................42 package dr awing ................................................................................................................ ........................52 recommended solder ing conditions............................................................................................... ...........53
edk2516cbbh preliminary data sheet e0300e90 (ver. 9.0) 4 electrical specifications ? all voltages are referenced to vss (gnd). ? after power up, wait more than 200 s and then, execute power on sequence and cbr (auto) refresh before proper device operation is achieved. absolute maximum ratings parameter symbol rating unit note voltage on any pin relative to vss vt ?1.0 to +2.6 v supply voltage relative to vss vdd ?1.0 to +2.6 v short circuit output current ios 50 ma power dissipation pd 1.0 w operating ambient temperature ta ?25 to +85 c storage temperature tstg ?55 to +125 c caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this speci fication. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended dc operating conditions (ta = ? 25 to +85 c) parameter symbol min typ max unit notes supply voltage vdd, vddq 1.65 1.8 1.95 v 1 vss, vssq 0 0 0 v input high voltage vih (dc) 0.8 vddq ? vddq + 0.3 v 2 input low voltage vil (dc) ?0.3 ? 0.3 v 3 input voltage level, ck and /ck inputs vin (dc) ?0.3 ? vddq + 0.3 v input differential cross point voltage, ck and /ck inputs vix (dc) 0.5 vddq ? 0.2v 0.5 vddq 0.5 vddq + 0.2v v input differential voltage, ck and /ck inputs vid (dc) 1.0 ? vddq + 0.6 v notes: 1. vddq must be equal to vdd. 2. vih (max.) = 2.6v (pulse width 5ns). 3. vil (min.) = ?1.0v (pulse width 5ns).
edk2516cbbh preliminary data sheet e0300e90 (ver. 9.0) 5 dc characteristics 1 (ta = ?25 to +85 c, vdd and vddq = 1.8v 0.15v, vss and vssq = 0v) parameter symbol grade max. unit test condition notes operating current idd1 55 ma burst length = 4 trc trc min., io = 0ma, one bank active 1 standby current in power down idd2p 0.5 ma cke vil max., tck = 15ns standby current in power down (input signal stable) idd2ps 0.4 ma cke vil max., tck = standby current in non power down idd2n 3.0 ma cke vih min., tck = 15ns, /cs vih min., input signals are changed one time during 30ns. standby current in non power down (input signal stable) idd2ns 2.0 ma cke vih min., tck = , input signals are stable. active standby current in power down idd3p 1.0 ma cke vil max., tck = 15ns active standby current in power down (input signal stable) idd3ps 0.8 ma cke vil max., tck = active standby current in non power down idd3n 15 ma cke vih min., tck = 15 ns, /cs vih min., input signals are changed one time during 30ns. active standby current in non power down (input signal stable) idd3ns 5 ma cke vih min., tck = , input signals are stable. burst operating current idd4 75 ma burst length = 8 tck tck min., iout = 0ma, all banks active 2 refresh current idd5 55 ma trc trc min. 3 standby current in deep power down mode idd7 10 a cke 0.2v self refresh current symbol grade typ max. unit condition notes pasr="000" (full) idd6 ? 400 a ta 85c +0c/ ? 20c, cke 0.2v 4 pasr="001" (2bk) ? 340 a pasr="010" (1bk) ? 320 a pasr="000" (full) idd6 200 ? a ta 45c, cke 0.2v 4 pasr="001" (2bk) 180 ? a pasr="010" (1bk) 160 ? a notes: 1. idd1 depends on output loading and cycle rates. specified values are obtained with the output open. in addition to this, idd1 is measured on conditi on that addresses are changed only one time during tck (min.). 2. idd4 depends on output loading and cycle rates. spec ified values are obtained with the output open. in addition to this, idd4 is measured on conditi on that addresses are changed only one time during tck (min.). 3. idd5 is measured on condit ion that addresses are changed only one time during tck (min.). 4. idd6 is specified when self refr esh state is maintained long enough un der the specified ta condition, after a busy sequence of read and write operations.
edk2516cbbh preliminary data sheet e0300e90 (ver. 9.0) 6 dc characteristics 2 (ta = ? 25 to +85 c, vdd and vddq = 1.8v 0.15v, vss and vssq = 0v) parameter symbol min. max. unit test condition notes input leakage current ili ?1.0 1.0 a 0 vin vddq output leakage current ilo ?1.5 1.5 a 0 vout vddq, dq = disable output high voltage voh vddq ? 0.2 ? v ioh = ? 0.1ma output low voltage vol ? 0.2 v iol = 0.1 ma pin capacitance (ta = +25c, vdd and vddq = 1.8v 0.15v) parameter symbol pins min. typ max. unit notes input capacitance ci1 ck, /ck 2.5 ? 3.5 pf 1 ci2 all other input pins 2.5 ? 3.5 pf 1 data input/output capacitance ci/o dq, dm, dqs 6.0 ? 7.5 pf 1, 2, notes: 1. these parameters are measured on conditions: f = 100mhz, vout = vddq/2, ? vout = 0.2v, ta = +25 c. 2. dout circuits are disabled.
edk2516cbbh preliminary data sheet e0300e90 (ver. 9.0) 7 ac characteristics (ta = ? 25 to +85 c, vdd and vddq = 1.8v 0.15v, vss and vssq = 0v) -10 parameter symbol min. max. unit notes clock cycle time (cl =2) tck ? ? ns (cl =3) tck 10 ? ns ck high-level width tch 0.45 0.55 tck ck low-level width tcl 0.45 0.55 tck dq output access time from ck, /ck tac 2.0 7.0 ns 2 dqs output access time from ck, /ck tdqsck 2.0 7.0 ns 2 dq-out high-impedance time from ck, /ck thz 2.0 7.0 ns 5 dq-out low-impedance time from ck, /ck tlz 2.0 7.0 ns 6 dqs-out high-impedance time from ck, /ck tdqshz 2.0 7.0 ns 5 dqs-out low-impedance time from ck, /ck tdqslz 2.0 7.0 ns 6 dqs to dq skew tdqsq ? 0.75 ns 3 dout valid window tdv 3.0 ? 4 dq and dm input setup time tds 1.0 ? ns 3 dq and dm input hold time tdh 1.0 ? ns 3 read preamble trpre 0.9 1.1 tck read postamble trpst 0.4 0.6 tck write preamble setup time twpres 0 ? ns write preamble twpre 0.25 ? tck write postamble twpst 0.4 0.6 tck 7 write command to first dqs latching transition tdqss 0.75 1.25 tck dqs falling edge to ck setup time tdss 0.2 ? tck dqs falling edge hold time from ck tdsh 0.2 ? tck dqs input high pulse width tdqsh 0.35 ? tck dqs input low pulse width tdqsl 0.35 ? tck address and control input setup time tis 1.5 ? ns 3 address and control input hold time tih 1.5 ? ns 3 mode register set command cycle time tmrd 2 ? tck active to precharge command period tras 60 120000 ns active to active/auto refresh command period trc 90 ? ns auto refresh to active/auto refresh command period trfc 110 ? ns active to read/write delay trcd 30 ? ns precharge to active command period trp 30 ? ns active to active command period trrd 20 ? ns write recovery time twr 20 ? ns self refresh exit period tsrex 120 ? ns average periodic refresh inte rval tref ? 7.8 s
edk2516cbbh preliminary data sheet e0300e90 (ver. 9.0) 8 notes: 1. on all ac measurements, we assume the te st conditions shown in ?test conditions? and full driver strength is assumed for the output load, that is both a6 and a5 of emrs is set to be ?l?. 2. this parameter defines the signal transition delay from the cr oss point of ck and /ck. the signal transition is defined to occur when the signal level crossing vref. 3. the timing reference level is vref. 4. output valid window is defined to be the period between two successi ve transition of data out signals. the signal transition is defined to occur when the signal level crossing vref. 5. thz and tdqshz are defined as dout transition delay from low-z to high-z at the end of read burst operation. the timing reference is cross point of ck and /ck. this parameter is not referred to a specific dout voltage level, but specify wh en the device output stops driving. 6. tlz and tdqslz are defined as dout transition delay from high-z to low-z at the beginning of read operation. this parameter is not referred to a spec ific dout voltage level, but specify when the device output begins driving. 7. the transition from low-z to hi gh-z is defined to occur when the device output stops drivi ng. a specific reference voltage to judge this transition is not given. test conditions parameter symbol value unit note input reference voltage vref 0.9 v 1 input high voltage vih (ac) 1.6 v input low voltage vil (ac) 0.2 v input differential voltage, ck and /ck inputs vid (ac) 1.4 v input differential cross point voltage, ck and /ck inputs vix (ac) 0.9 v input signal slew rate slew 1 v/ns note: 1. internally generated. tck tch tdqlz tac tcl ck /ck vix vref (=0.9v) dqout (dqout) q1 q2 vref (=0.9v) t slew rate = t (v ih ? v il ) vih (=1.6v) vil (=0.2v) test condition (wave form and timing reference) z0 = 50 cl = 30 pf output load
edk2516cbbh preliminary data sheet e0300e90 (ver. 9.0) 9 timing parameter measured in clock cycle number of clock cycle tck 10ns parameter symbol min. max. unit write to pre-charge command delay (same bank) twpd 3 + bl/2 ? tck read to pre-charge command delay (same bank) trpd bl/2 ? tck write to read command delay (to input all data) twrd 2 + bl/2 ? tck burst stop command to write command delay (cl = 3) tbstw 3 ? tck burst stop command to dq high-z (cl = 3) tbstz 3 ? tck read command to write command delay (to output all data) (cl = 3) trwd 3 + bl/2 ? tck pre-charge command to high-z (cl = 3) thzp 3 ? tck write command to data in latency twcd 1 ? tck write recovery twr 2 ? tck dm to data in latency tdmd 0 ? tck mode register set command cycle time tmrd 2 ? tck self refresh exit to non-column command tsrex 12 ? tck auto refresh period trfc 11 ? tck power down entry tpden 1 ? tck power down exit to command input tpdex 1 ? tck
edk2516cbbh preliminary data sheet e0300e90 (ver. 9.0) 10 block diagram a0 to a12, ba0, ba1 /cs /ras /cas /we command decoder input & output buffer latch circuit data control circuit column decoder row decoder memory cell array bank 0 sense amp. bank 1 bank 2 bank 3 control logic column address buffer and burst counter row address buffer and refresh counter mode register clock generator dq ck /ck cke dqs dm
edk2516cbbh preliminary data sheet e0300e90 (ver. 9.0) 11 pin function ck, /ck (input pins) the ck and the /ck are the master clock inputs. all in puts except dms, dqss and dqs are referred to the cross point of the ck rising edge and the /c k falling edge. when a read operation, dqss and dqs are referred to the cross point of the ck and the /ck. when a write operation, dms and dqs are re ferred to the cross point of the dqs and the vref level. dqss for write operation are referred to the cross point of the ck and the /ck. the other input signals are referred at ck rising edge. /cs (input pin) when /cs is low, commands and data can be input. when /cs is high, all inputs are ignored. however, internal operations (bank active, burst operations, etc.) are held. /ras, /cas, and /we (input pins) these pins define operating commands (re ad, write, etc.) depending on the comb inations of their voltage levels. see "command operation". a0 to a12 (input pins) row address (ax0 to ax12) is determined by the a0 to the a12 level at the cross point of the ck rising edge and the /ck falling edge in a bank active command cycle. column address (see ?address pins table?) is loaded via the a0 to the a8 at the cross point of the ck rising edge and the /ck falling edge in a read or a write command cycle. this column address becomes the starti ng address of a burst operation. [address pins table] address (a0 to a12) part number row address column address edk2516cbbh ax0 to ax12 ay0 to ay8 a10 (ap) (input pin) a10 defines the precharge mode when a precharge command, a read command or a write command is issued. if a10 = high when a precharge command is issued, all ban ks are precharged. if a10 = low when a precharge command is issued, only the bank that is selected by ba1/ba0 is precharged. if a10 = high when read or write command, auto-precharge function is enabled. ba0 and ba1 (input pins) ba0 and ba1 are bank select signals (ba). the memory arra y is divided into bank 0, bank 1, bank 2 and bank 3. (see bank select signal table) [bank select signal table] ba0 ba1 bank 0 l l bank 1 h l bank 2 l h bank 3 h h remark: h: vih. l: vil.
edk2516cbbh preliminary data sheet e0300e90 (ver. 9.0) 12 cke (input pin) cke controls power down mode, self-refresh function a nd deep power down function with other command inputs. the cke level must be kept for 1 ck cycle at least, that is , if cke changes at the cross point of the ck rising edge and the /ck falling edge with proper setup time tis, by the next ck rising edge cke level must be kept with proper hold time tih. dq0 todq15 (input/output pins) data are input to and output from these pins. udqs, ldqs (input and output pin): dqs provides the read data strobes (as output) and the write data strobes (as input). ldqs is the strobe signals specific for the lower dq signals (dq0 to dq7). udqs is the strobe signals specific for the upper dq signals (dq8 to dq15). udm, ldm (input pin) dm is the reference signals of the dat a input mask function. dm is sampl ed at the cross point of dqs and vref. ldm controls the lower dq signals (dq0 to dq7). udm controls the upper dq signals (dq7 to dq15). vdd, vss, vddq, vssq (power supply) vdd and vss are power supply pins for internal circuits . vddq and vssq are power supply pins for the output buffers. vdd must be equal to vddq.
edk2516cbbh preliminary data sheet e0300e90 (ver. 9.0) 13 command operation command truth table the ddr mobile ram recognizes the following commands spec ified by the /cs, /ras, /cas, /we and address pins. all other combinations than those in the table below are illegal. cke command symbol n ? 1 n /cs /ras /cas /we ba1 ba0 ap address ignore command desl h h h no operation nop h h l h h h burst stop in read command bst h h l h h l column address and read command read h h l h l h v v l v read with auto-precharge reada h h l h l h v v h v column address and write command writ h h l h l l v v l v write with auto-precharge writa h h l h l l v v h v row address strobe and bank active act h h l l h h v v v v precharge select bank pre h h l l h l v v l precharge all bank pall h h l l h l h refresh ref h h l l l h self h l l l l h mode register set mrs h h l l l l l l l v emrs h h l l l l h l l v remark: h: vih. l: vil. : vih or vil v: valid address input note: the cke level must be kept for 1 ck cycle at least. ignore command [desl] when /cs is high at the cross point of the ck rising edge and the vref level, all input signals are neglected and internal status is held. no operation [nop] as long as this command is input at the cross point of the ck rising ed ge and the vref level, address and data input are neglected and internal status is held. burst stop in read operation [bst] this command stops a burst read o peration, which is not applicable for a burst write operation. column address strobe and read command [read] this command starts a read operation. the start address of the burst read is determined by the column address (see ?address pins table? in pin function) and the bank select address. after the comple tion of the read operation, all output buffers become high-z. read with auto-precharge [reada] this command starts a read operation. after completion of the read operation, precharg e is automatically executed. column address strobe and write command [writ] this command starts a write operation. the start address of the burst write is determined by the column address (see ?address pins table? in pin function) and the bank select address. write with auto-precharge [writa] this command starts a write operation. after completion of the write operation, prechar ge is automatically executed.
edk2516cbbh preliminary data sheet e0300e90 (ver. 9.0) 14 row address strobe and bank activate [act] this command activates the bank that is selected by ba0 and ba1 and determines the row address (ax0 to ax12). (see bank select signal table) precharge selected bank [pre] this command starts precharge operation for the bank sele cted by ba0 and ba1. (see bank select signal table) [bank select signal table] ba0 ba1 bank 0 l l bank 1 h l bank 2 l h bank 3 h h remark: h: vih. l: vil. precharge all banks [pall] this command starts a precharge operation for all banks. refresh [ref/self] this command starts a refresh operation. there are two types of refresh oper ation, one is auto -refresh, and another is self-refresh. for details, refe r to the cke truth table section. mode register set/extended mode register set [mrs/emrs] the ddr mobile ram has the two mode registers, the mode register and the extended mode register, to defines how it works. the both m ode registers are set through the address pins (the a0 to the a12, ba0 to ba1) in the mode register set cycle. for details, refer to "mode register and extended mode register set".
edk2516cbbh preliminary data sheet e0300e90 (ver. 9.0) 15 function truth table the following tables show the operations that are perf ormed when each command is issued in each state of the ddr mobile ram. function truth table (1) current state /cs /ras /cas /we address command operation next state precharging* 1 h desl nop idle l h h h nop nop idle l h h l bst illegal* 11 ? l h l h ba, ca, a10 read/reada illegal* 11 ? l h l l ba, ca, a10 writ/writa illegal* 11 ? l l h h ba, ra act illegal* 11 ? l l h l ba, a10 pre, pall nop idle l l l illegal ? idle* 2 h desl nop idle l h h h nop nop idle l h h l bst nop idle l h l h ba, ca, a10 read/reada illegal* 11 ? l h l l ba, ca, a10 writ/writa illegal* 11 ? l l h h ba, ra act activating active l l h l ba, a10 pre, pall nop idle l l l h ref, self refresh/ self refresh* 12 idle / self refresh l l l l mode mrs mode register set* 12 idle refresh (auto-refresh)* 3 h desl nop idle l h h h nop nop idle h h h l bst illegal ? l h l illegal ? l l illegal ?
edk2516cbbh preliminary data sheet e0300e90 (ver. 9.0) 16 function truth table (2) current state /cs /ras /cas /we address command operation next state activating* 4 h desl nop active l h h h nop nop active l h h l bst illegal* 11 ? l h l h ba, ca, a10 read/reada illegal* 11 ? l h l l ba, ca, a10 writ/writa illegal* 11 ? l l h h ba, ra act illegal* 11 ? l l h l ba, a10 pre, pall illegal* 11 ? l l l illegal ? active* 5 h desl nop active l h h h nop nop active l h h l bst nop active l h l h ba, ca, a10 read/reada starting read operation read/reada l h l l ba, ca, a10 writ/writa starting write operation write recovering/ precharging l l h h ba, ra act illegal* 11 ? l l h l ba, a10 pre, pall pre-charge idle l l l illegal ? read* 6 h desl nop active l h h h nop nop active l h h l bst bst active l h l h ba, ca, a10 read/reada interrupting burst read operation to start new read active l h l l ba, ca, a10 writ/writa illegal* 13 ? l l h h ba, ra act illegal* 11 ? l l h l ba, a10 pre, pall interrupting burst read operation to start pre- charge precharging l l l illegal ?
edk2516cbbh preliminary data sheet e0300e90 (ver. 9.0) 17 function truth table (3) current state /cs /ras /cas /we address command operation next state read with auto-pre- charge* 7 h desl nop precharging l h h h nop nop precharging l h h l bst illegal ? l h l h ba, ca, a10 read/reada illegal ? l h l l ba, ca, a10 writ/writa illegal ? l l h h ba, ra act illegal* 11 ? l l h l ba, a10 pre, pall illegal* 11 ? l l l illegal ? write* 8 h desl nop write recovering l h h h nop nop write recovering l h h l bst illegal ? l h l h ba, ca, a10 read/reada interrupting burst write operation to start read operation. read/reada l h l l ba, ca, a10 writ/writa interrupting burst write operation to start new write operation. write/writea l l h h ba, ra act illegal* 11 ? l l h l ba, a10 pre, pall interrupting write operation to start pre- charge. idle l l l illegal ? write recovering* 9 h desl nop active l h h h nop nop active l h h l bst illegal ? l h l h ba, ca, a10 read/reada starting read operation. read/reada l h l l ba, ca, a10 writ/writa starting new write operation. write/writea l l h h ba, ra act illegal* 11 ? l l h l ba, a10 pre/pall illegal* 11 ? l l l illegal ?
edk2516cbbh preliminary data sheet e0300e90 (ver. 9.0) 18 function truth table (4) current state /cs /ras /cas /we address command operation next state write with auto- pre-charge* 10 h desl nop precharging l h h h nop nop precharging l h h l bst illegal ? l h l h ba, ca, a10 read/reada illegal ? l h l l ba, ca, a10 writ/writ a illegal ? l l h h ba, ra act illegal* 11 ? l l h l ba, a10 pre, pall illegal* 11 ? l l l illegal ? remark: h: vih. l: vil. : vih or vil notes: 1. the ddr mobile ram is in "precharging" state for trp after precharge command is issued. 2. the ddr mobile ram reaches "idle" stat e trp after precharge command is issued. 3. the ddr mobile ram is in "refresh" stat e for trc after auto-refresh command is issued. 4. the ddr mobile ram is in "activating" state for trcd after act command is issued. 5. the ddr mobile ram is in "active" state after "activating" is completed. 6. the ddr mobile ram is in "read" state until bur st data have been output and dq output circuits are turned off. 7. the ddr mobile ram is in "read with auto-prec harge" from reada command until burst data has been output and dq output circuits are turned off. 8. the ddr mobile ram is in "write" state from writ command to the last burst data are input. 9. the ddr mobile ram is in "write recove ring" for twr after the last data are input. 10. the ddr mobile ram is in "write with auto-precharge" until twr after the last data has been input. 11. this command may be issued for other banks, depending on the st ate of the banks. 12. all banks must be in "idle". 13. before executing a write command to stop the pr eceding burst read operati on, bst command must be issued.
edk2516cbbh preliminary data sheet e0300e90 (ver. 9.0) 19 cke truth table cke current state command n ? 1 n /cs /ras /cas /we address notes idle auto-refresh command (ref) h h l l l h 2 idle self-refresh entry (self) h l l l l h 2 h l l h h h idle power down entry (pden) h l h idle deep power down entry (dpden) h l l h h l l h l h h h self refresh self refresh exit (selfx) l h h l h l h h h power down power down exit (pdex) l h h deep power down power down exit (dpdex) l h notes: 1. h: vih . l: vil : vih or vil . 2. all the banks must be in id le before executing this command. 3. the cke level must be kept for 1 clock cycle at least. auto-refresh command [ref] this command executes auto-refresh. the bank and t he row addresses to be refreshed are internally determined by the internal refresh controller. the output buffer be comes high-z after auto-refresh start. precharge has been completed automatically after the auto-refresh. the act or mrs command can be issued trfc after the last auto- refresh command. the average refresh cycle is 7.8 s. to allow for improved efficiency in scheduling, some flexibility in the absolute refresh interval (64ms) is provided. a maximum of eight auto-refresh commands c an be posted to the ddr mobile ram or the maximum absolute interval between any auto-refresh command and the next auto-refresh command is 9 tref. self-refresh entry [self] this command starts self-refresh. the se lf-refresh operation continues as long as cke is held low. during the self- refresh operation, all row addresses ar e repeated refreshing by the internal refresh controller. a self-refresh is terminated by a self-refresh exit command. power down mode entry [pden] tpden (= 1 cycle) after the cycle when [pden] is issued, the ddr mobile ram enters into power-down mode. in power down mode, power consumption is suppressed by deactivating the input initial circuit. power down mode continues while cke is held low. no internal refr esh operation occurs during the power down mode. deep power down entry [dpden] after the command execution, deep power down mode continues while cke remains low. before executing deep power down, all bank s must be precharged or in idle state. self-refresh exit [selfx] this command is executed to exit fr om self-refresh mode. trc + 3tck after [selfx], non-read commands can be executed power down exit [pdex] the ddr mobile ram can exit from power down mode tpdex (1 cycle min.) after the cycle when [pdex] is issued.
edk2516cbbh preliminary data sheet e0300e90 (ver. 9.0) 20 deep power down exit [dpdex] as cke goes high in the deep power down mode, t he ddr mobile ram exit from the deep power down mode through deep power down exiting sequence. simplified state diagram cke cke precharge auto precharge pre read with auto precharge read bst pre (precharge termination) pre (precharge termination) act mrs ref cke cke self self exit idle mode register set extended mode register set cbr (auto) refresh row active self refresh power down active power down precharge emrs read reada write writea power on write read automatic sequence manual input deep power down exit sequence read write write with deep power down dpden deep power down exit sequence
edk2516cbbh preliminary data sheet e0300e90 (ver. 9.0) 21 operation of the ddr mobile ram initialization the ddr mobile ram is initialized in the power-on sequence according to the following. (1) to stabilize internal circuits, when power is applied, a 200 s or longer pause must precede any signal toggling. (2) after the pause, all banks must be precharged us ing the precharge command (the precharge all banks command is convenient). (3) once the precharge is completed and the minimum trp is satisfied, two or more auto refresh must be performed. (4) both the mode register and the extended mode register must be programmed. after the mode register set cycle or the extended mode register set cycle, tm rd (2 clocks minimum) pause must be satisfied. remarks: 1 the sequence of auto refresh, m ode register programming and extended m ode register programming above may be transposed. 2 cke and dm must be held high until the precharge command is issued to ensure data-bus high-z. mode register and extended mode register set there are two mode registers, the m ode register and the extended mode regi ster so as to define the operating mode. parameters are set to both through the a0 to the a12 and ba0 and ba1 pins by the mode register set command [mrs] or the extended mode register set co mmand [emrs]. the mode regi ster and the extended mode register are set by inputting signal via the a0 to the a12 and ba0 and ba1 pins during mode register set cycles. ba0 and ba1 determine which one of the mode register or the extended mode regist er are set. prior to a read or a write operation, the mode register must be set. mode register the mode register has three fields; options : a12 through a7 /cas latency : a6 through a4 wrap type : a3 burst length : a2 through a0 following mode register programming, no command can be issued before at least 2 clocks have elapsed. /cas latency /cas latency must be set to 3. burst length burst length is the number of words that will be output or input in a read or write cycle. after a read burst is completed, the output bus will become high-z. t he burst length is progra mmable as 2, 4, and 8. wrap type (burst sequence) the wrap type specifies the order in which the burst data will be addressed. this order is programmable as either ?sequential? or ?interleave?. ?burst operation? shows the addressing sequenc e for each burst length for each wrap type.
edk2516cbbh preliminary data sheet e0300e90 (ver. 9.0) 22 extended mode register the extended mode register has four fields; options : a12 through a10, a8, a7, a4 and a3 driver strength : a6 and a5 auto temperature compensated self refresh: a9 partial array self refresh : a2 through a0 following extended mode register progr amming, no command can be issued befor e at least 2 clocks have elapsed. driver strength by setting specific parameter on a6 and a5, drivin g capability of data output drivers is selected. auto temperature compensated self refresh (atcsr) with the built-in temperature sens or, the internal self refresh frequency is controlled autonomously. partial array self refresh memory array size to be re freshed during self refresh operation is pr ogrammable in order to reduce power. data outside the defined area will not be retained during self refresh. deep power down exit sequence in order to exit from the deep powe r down mode and enter into the idle mode, the following sequence is needed, which is similar to the power-on sequence. (1) a 200 s or longer pause must precede any command other than ignore command (desl). (2) after the pause, all banks must be precharged usin g the precharge command (the precharge all banks command is convenient). (3) once the precharge is completed and the minimum trp is satisfied, two or more auto refresh must be performed. (4) both the mode register and the extended mode register must be programmed. after the mode register set cycle or the extended mode register set cycle, tm rd (2 clocks minimum) pause must be satisfied. remarks: 1 the sequence of auto refresh, m ode register programming and extended m ode register programming above may be transposed. 2 cke and dm must be held high until the precharge command is issued to ensure data-bus high-z.
edk2516cbbh preliminary data sheet e0300e90 (ver. 9.0) 23 mode register definition wt = 1 r 2 4 8 r r r r bl wt 0 0 0 0 0 mode register set wt = 0 r 2 4 8 r r r r bits2-0 000 001 010 011 100 101 110 111 burst length sequential interleave 0 1 wrap type a0 a1 a2 a3 a4 a5 a7 a6 a8 a9 a10 a11 0 0 remark r : reserved ltmode pasr ds 0 0 00 extended mode register set refresh array all banks bank a & bank b (ba1=0) bank a (ba0=ba1=0) r r r r r bits2-0 000 001 010 011 100 101 110 111 partial array self refresh atcsr enable r bit9 0 1 driver strength ba1 ba0 1 0 /cas latency r r r 3 r r r r bits6-4 000 001 010 011 100 101 110 111 latency mode a12 0 a0 a1 a2 a3 a4 a5 a7 a6 a8 a9 a10 a11 ba1 ba0 atcsr strength normal 1/2 strength 1/4 strength 1/8 strength bits6-5 00 01 10 11 atcsr a12 0 0 0
edk2516cbbh preliminary data sheet e0300e90 (ver. 9.0) 24 burst operation the burst type (bt) and the first three bits of t he column address determine the order of a data out. a2 a1 a0 addressing(decimal) 00 0 00 1 01 0 01 1 11 1 interleave sequence 10 0 11 0 10 1 starting ad. 0, 1, 2, 3, 4, 5, 6, 7, 1, 2, 3, 4, 5, 6, 7, 2, 3, 4, 5, 6, 7, 3, 4, 5, 6, 7, 4, 5, 6, 7, 5, 6, 7, 6, 7, 7, 0, 0, 1, 0, 1, 2, 0, 1, 2, 3, 0, 1, 2, 3, 4, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 6, 0, 1, 2, 3, 4, 5, 6, 7, 1, 0, 3, 2, 5, 4, 7, 2, 3, 0, 1, 6, 7, 3, 2, 1, 0, 7, 4, 5, 6, 7, 5, 4, 7, 6, 7, 7, 6, 4, 5, 6, 5, 4, 0, 1, 2, 3, 6, 1, 0, 3, 2, 4, 5, 2, 3, 0, 1, 6, 5, 4, 3, 2, 1, 0, burst length = 8 a1 a0 addressing(decimal) 00 01 10 11 interleave sequence starting ad. 0, 1, 2, 3, 1, 2, 3, 0, 2, 3, 0, 1, 3, 0, 1, 2, 0, 1, 2, 3, 1, 0, 3, 2, 2, 3, 0, 1, 3, 2, 1, 0, burst length = 4 a0 addressing(decimal) 0 1 interleave sequence starting ad. 0, 1, 1, 0, 0, 1, 1, 0, burst length = 2
edk2516cbbh preliminary data sheet e0300e90 (ver. 9.0) 25 read/write operations bank active a read or a write operation begins with the bank active command [act]. the bank active command determines a bank address and a row address. for the bank and the row, a read or a write command can be issued trcd after the act is issued. read operation the burst length (bl), the /cas latency (cl) and the burst type (bt) of the mode register are referred when a read command is issued. the burst length (bl) determines the length of a sequent ial output data by the read command that can be set to 2, 4, or 8. the starting address of t he burst read is defined by the column address, the bank select address which is loaded via the a0 to a12 and ba0 and ba1 pins in the cycle when the read command is issued. the data output timing is characterized by cl and tac. the read burst start cl tck + tac (ns) after the clock rising edge where the read command is latched. the ddr mobile ram outputs the data strobe through dqs pins simultaneously with data. trpre prior to the first risi ng edge of the data str obe, the dqs pins are driven low from high-z state. this low period of dqs is referred as read preamble. the burst data are output coincidentally at both the rising and falling edge of the data st robe. the dq pins become high-z in the next cycle after the burst read operation completed. trpst from the last falling edge of the data strobe, the dqs pins become high-z. this low period of dqs is referred as read postamble. out0 out1 out0 out1 out2 out3 out0 out1 out2 out3 out4 out5 out6 out7 ck /ck address dqs dq bl = 2 bl = 4 bl = 8 command cl = 3 bl: burst length trcd trpst act nop nop nop read row column trpre read operation (burst length)
edk2516cbbh preliminary data sheet e0300e90 (ver. 9.0) 26 ck /ck vtt vtt dqs dq command t0 t0.5 t1 t1.5 t2 t2.5 t3 t3.5 t4 t4.5 t5 t5.5 out0 out1 out2 out3 tac,tdqsck read nop trpre trpst read operation (/cas latency) write operation the burst length (bl) and the burst type (bt) of the mode register are referr ed when a write command is issued. the burst length (bl) determines the length of a sequential dat a input by the write command that can be set to 2, 4, or 8. the latency from write command to data input is fixed to 1. the starting address of the burst read is defined by the column address, the bank select addr ess which is loaded via the a0 to a12, ba0 to ba1 pins in the cycle when the write command is issued. dqs should be input as t he strobe for the input-data and dm as well during burst operation. twpre prior to the first rising edge of dqs, dqs must be set to low. twpst after the last falling edge of dqs, the dqs pins can be changed to high-z. the leading low period of dqs is referred as write preamble. the last low period of dqs is referred as write postamble. in1 in0 in1 in2 in3 in0 in1 in2 in3 in4 in5 in6 in7 ck /ck address dqs dq bl = 2 bl = 4 bl = 8 command bl: burst length in0 act nop nop nop writ twpre twpres row column trcd twpst write operation
edk2516cbbh preliminary data sheet e0300e90 (ver. 9.0) 27 burst stop burst stop command during burst read the burst stop (bst) command is used to stop data output during a burst read. the bst command stops the burst read and sets all output buffers to high-z. tbstz (= cl) cycles after a bst command issued, all dq and dqs pins become high-z. the bst command is not supported for the burst wr ite operation. note t hat bank address is not referred when this command is executed. ck /ck dqs dq command t0 t0.5 t1 t1.5 t2 t2.5 t3 t3.5 t4 t4.5 t5 t5.5 out0 out1 cl: /cas latency read bst nop tbstz burst stop during a read operation
edk2516cbbh preliminary data sheet e0300e90 (ver. 9.0) 28 auto-precharge read with auto-precharge the precharge is automatically performed after completing a read operation. the precharge starts trpd (bl/2) cycle after reada command input. tras lock out mechanism for reada allows a read command with auto precharge to be issued to a bank that has been activa ted (opened) but has not yet satisfied the tras (min) specification. a column command to the other active bank can be issued the next cycle after the last data output. read with auto-precharge command does not limit row commands execution for other bank. out0 out1 out2 out3 ck /ck dq command trp (min) trcd (min) act note: internal auto-precharge starts at the timing indicated by " ". nop 2 cycles (= bl/2) reada act dqs tac,tdqsck trpd tras (min) read with auto-precharge write with auto-precharge the precharge is automatically performed after completing a burst write operation. the precharge operation is started twpd (= bl/2 + 3) cycles after writa command issued. a column command to the other banks can be issued the ne xt cycle after the internal precharge command issued. write with auto-precharge command does not limit row commands execution for other bank. in1 in2 in3 in4 ck /ck dq command dm tras (min) trcd (min) trp dqs act writa act bl/2 + 3 cycles note: internal auto-precharge starts at the timing indicated by " ". bl = 4 nop nop burst write (bl = 4)
edk2516cbbh preliminary data sheet e0300e90 (ver. 9.0) 29 the concurrent auto precharge the ddr mobile ram supports the concurrent auto precharge feature, a read with auto-pr echarge or a write with auto-precharge, can be followed by any command to the ot her banks, as long as that command does not interrupt the read or write data transfer, and a ll other related limitations apply (e .g. contention between read data and write data must be avoided.) the minimum delay from a read or write command with auto precharge, to a command to a different bank, is summarized below. from command to command (different bank, non- interrupting command) minimum delay (concurrent ap supported) units read w/ap read or read w/ap bl/2 tck write or write w/ap cl (rounded up)+ (bl/2) tck precharge or activate 1 tck write w/ap read or read w/ap 1 + (bl/2) + twtr tck write or write w/ap bl/2 tck precharge or activate 1 tck
edk2516cbbh preliminary data sheet e0300e90 (ver. 9.0) 30 command intervals a read command to the consecutive read command interval destination row of the consecutive read command bank address row address state operation 1. same same active the consecutive read can be performed afte r an interval of no less than 1 cycle to interrupt the preceding read operation. 2. same different ? precharge the bank to interrupt the preceding read operation. trp after the precharge command, issue the act command. trcd after the act command, the consecutive read command can be iss ued. see ?a read command to the consecutive precharge interval? section. 3. different any active the consecutive read can be performed afte r an interval of no less than 1 cycle to interrupt the preceding read operation. idle precharge the bank without interrupting the preceding read operation. trp after the precharge command, issue the act command. trcd after the act command, the consecutive read command can be issued. out a0 out a1 out b0 out b1 out b2 out b3 ck /ck address ba dq dqs command tn t0 tn+1 tn+2 tn+3 tn+4 tn+5 tn+6 bank0 active cl = 3 bl = 4 bank0 nop act nop read row read column = a read column = b read column = a dout column = b dout column a column b read to read command interval (same row address in the same bank)* note: n 3
edk2516cbbh preliminary data sheet e0300e90 (ver. 9.0) 31 out a0 out a1 out b0 out b1 out b3 ck /ck address ba dq dqs command t1 t0 t2 bank0 active bank3 active bank0 read bank3 read cl = 3 bl = 4 nop act nop nop row0 act read row1 column a read column b column = a read column = b read bank3 dout bank0 dout out b2 tn tn+1 tn+2 tn+3 tn+4 tn+5 tn+6 read to read command interval (different bank)* note: n 3
edk2516cbbh preliminary data sheet e0300e90 (ver. 9.0) 32 a write command to the consecutive write command interval destination row of the consecutive write command bank address row address state operation 1. same same active the consecutive write can be performed afte r an interval of no less than 1 cycle to interrupt the preceding write operation. 2. same different ? precharge the bank to interrupt the preceding write operation. trp after the precharge command, issue the act command. trcd after the act command, the consecutive write command can be iss ued. see ?a write command to the consecutive precharge interval? section. 3. different any active the consecutive write can be performed afte r an interval of no less than 1 cycle to interrupt the preceding write operation. idle precharge the bank without interrupting the preceding write operation. trp after the precharge command, issue the act command. trcd after the act command, the consecutive write command can be issued. ina0 ina1 inb0 inb1 inb2 inb3 ck /ck address ba dq command t0 tn+1 tn tn+2 tn+3 tn+4 tn+5 tn+6 bank0 active bl = 4 bank0 nop dqs act nop writ row column a writ column b column = a write column = b write write to write command interval (same row address in the same bank)
edk2516cbbh preliminary data sheet e0300e90 (ver. 9.0) 33 ina0 ina1 inb0 inb1 inb2 inb3 ck /ck address ba dq command t1 t0 t2 tn tn+1 tn+2 tn+3 tn+4 tn+5 bank0 active bank3 active bank0 write bank3 write bl = 4 bank0, 3 nop dqs act nop act row0 row1 column a nop writ column b writ write to write command interval (different bank)
edk2516cbbh preliminary data sheet e0300e90 (ver. 9.0) 34 a read command to the consecutive write command interval with the bst command destination row of the consecutive write command bank address row address state operation 1. same same active issue the bst command. tbstw ( tbstz) after the bst command, the consecutive write command can be issued. 2. same different ? precharge the bank to interrupt the preceding read operation. trp after the precharge command, issue the act command. trcd after the act command, the consecutive write command can be i ssued. see ?a read command to the consecutive precharge interval? section. 3. different any active issue the bst command. tbstw ( tbstz) after the bst command, the consecutive write command can be issued. idle precharge the bank independently of the preceding read operation. trp after the precharge command, issue the act command. trcd after the act command, the consecutive write command can be issued. out0 out1 in0 in1 in2 in3 ck /ck dm dq command t1 t0 t2 t3 t4 t5 t6 t7 t8 bl = 4 cl = 3 dqs output input tbstw ( tbstz) high-z read writ bst nop nop tbstz (= cl) read to write command interval
edk2516cbbh preliminary data sheet e0300e90 (ver. 9.0) 35 a write command to the consecutive read command interval: to complete the burst operation destination row of the consecutive read command bank address row address state operation 1. same same active to complete the burst operation, the consecutive read command should be performed twrd (= bl/ 2 + 2) after the write command. 2. same different ? precharge the bank twpd after the preceding write command. trp after the precharge command, issue the act command. trcd after the act command, the consecutive read command can be i ssued. see ?a read command to the consecutive precharge interval? section. 3. different any active to complete a burst operation, the consecutive read command should be performed twrd (= bl/ 2 + 2) after the write command. idle precharge the bank independently of the preceding write operation. trp after the precharge command, issue the act command. trcd after the act command, the consecutive read command can be issued. in0 in1 in2 in3 out2 out0 out1 ck /ck dm dq command t1 t0 t2 t3 t4 t5 t6 t7 t8 bl = 4 cl = 3 twrd (min) dqs input output bl/2 + 2 cycle writ nop nop read write to read command interval
edk2516cbbh preliminary data sheet e0300e90 (ver. 9.0) 36 a write command to the consecutive read command interval: to interrupt the write operation destination row of the consecutive read command bank address row address state operation 1. same same active dm must be input 1 cycle prior to the read command input to prevent from being written invalid data. in case, the read command is input in the next cycle of the write command, dm is not necessary. 2. same different ? ?* 1 3. different any active dm must be input 1 cycle prior to the read command input to prevent from being written invalid data. in case, the read command is input in the next cycle of the write command, dm is not necessary. idle ?* 1 note: 1. precharge must be preceded to read command. therefore read command ca n not interrupt the write operation in this case. write to read command interval (same bank, same row address) in0 in1 in2 out0 out1 out3 ck /ck dm dq command t1 t0 t2 t3 t4 t5 t6 t7 t8 bl = 4 cl = 3 dqs data masked read nop writ high-z high-z out2 [write to read delay = 1 clock cycle]
edk2516cbbh preliminary data sheet e0300e90 (ver. 9.0) 37 in0 in1 in2 in3 out1 out2 out3 ck /ck dm dq command t1 t0 t2 t3 t4 t5 t6 t7 t8 bl = 4 cl = 3 dqs data masked read nop nop writ high-z high-z out0 [write to read delay = 2 clock cycle] in0 in1 in2 in3 out0 out1 out2 out3 ck /ck dm dq command t1 t0 t2 t3 t4 t5 t6 t7 t8 bl = 4 cl = 3 dqs data masked read writ nop nop [write to read delay = 3 clock cycle]
edk2516cbbh preliminary data sheet e0300e90 (ver. 9.0) 38 a read command to the consecutive precharge command interval (same bank): to output all data to complete a burst read operation and get a burst length of data, the consecutive pr echarge command must be issued trpd (= bl/ 2 cycles) after the read command is issued. ck /ck dq dqs command t1 t0 t2 t3 t4 t5 t6 t7 t8 trpd = bl/2 nop nop nop pre/ pall out0 out1 out2 out3 read read to precharge command interval (same bank): to output all data (cl = 3, bl = 4) read to precharge command interval (same bank): to stop output data a burst data output can be in terrupted with a precharge command. all dq pins and dqs pins become high-z thzp (= cl) after the precharge command. out0 ck /ck dq dqs command t1 t0 t2 t3 t4 t5 t6 t7 t8 high-z high-z thzp read nop nop pre/pall out1 read to precharge command interval (same bank): to stop output data (cl = 3, bl = 4, 8)
edk2516cbbh preliminary data sheet e0300e90 (ver. 9.0) 39 a write command to the consecutive precharge command interval (same bank) the minimum interval twpd ((bl/2 + 3) cycles) is necessary between the write command and the precharge command. in0 in1 in2 in3 ck /ck dq dm dqs command t1 t0 t2 t3 t4 t5 t6 t7 last data input twpd writ nop nop twr pre/pall write to precharge command interval (same bank) (bl = 4)
edk2516cbbh preliminary data sheet e0300e90 (ver. 9.0) 40 bank active command interval destination row of the consecutive act command bank address row address state operation 1. same any active two successive act commands can be issued at trc interval. in between two successive act operations, precharge command should be executed. 2. different any active precharge the bank. trp after the precharge command, the consecutive act command can be issued. idle trrd after an act command, the next act command can be issued. ck /ck command ba trc address actv trrd bank0 active bank3 active bank0 precharge bank0 active pre act row: 0 nop nop nop act act row: 1 row: 0 bank active to bank active mode register set to bank-active command interval the interval between setting the mode register and ex ecuting a bank-active command must be no less than tmrd. ck /ck command address nop nop mrs act tmrd mode register set bank3 active code bs and row
edk2516cbbh preliminary data sheet e0300e90 (ver. 9.0) 41 dm control dm can mask input data. by setting dm to low, data c an be written. udm and ldm can mask the upper and lower byte of input data, respectively. when dm is set to hi gh, the corresponding data is no t written, and the previous data is held. the latency between dm input and enabling/disabling mask function is 0. mask mask dqs dq dm t1 t2 t3 t4 t5 t6 write mask latency = 0 dm control
edk2516cbbh preliminary data sheet e0300e90 (ver. 9.0) 42 timing waveforms command and addresses input timing definition ck /ck vref command (/ras, /cas, /we, /cs) address tis tis tih tih vref read timing definition (1) ck /ck command dq (output) dqs high-z high-z high-z high-z read tdqslz (max.) tdqslz (min.) tdqlz (max.) tdqlz (min.) tdqshz (max.) tdqshz (min.) read timing definition (2) ck /ck high-z high-z high-z high-z tac (min.) tac (max.) tdqsck tdqsq tdqsq tdv dq (output dqs (output)
edk2516cbbh preliminary data sheet e0300e90 (ver. 9.0) 43 write timing definition /ck ck dqs dm vref vref vref dq (din) tds tdh tdqss twpre twpres tds tdh tck tdsh tdss tdss tdqsl tdqsh twpst
edk2516cbbh preliminary data sheet e0300e90 (ver. 9.0) 44 power on sequence ck /ck cke /cs /ras /cas /we ba1 a10 address dm dq h igh -z tmrd tmrd address key address key 2 refresh cycles are necessary trfc trfc precharge all banks command is necessary mode register set command is necessary extended mode register set command is necessary cbr (auto) refresh command is necessary activate command cbr (auto) refresh command is necessary ba0 clock cycle is necessary trp vih vih
edk2516cbbh preliminary data sheet e0300e90 (ver. 9.0) 45 read cycle bank 0 active bank 0 read bank 0 precharge cl = 3 bl = 4 bank0 access = vih or vil bank 0 active bank 0 read bank 0 precharge tis tih tch tck tcl tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih /ras a10 address high-z high-z /cs cke ck /ck /cas /we ba dqs dq (output) dm vih trcd tras trp trc trpst trpre
edk2516cbbh preliminary data sheet e0300e90 (ver. 9.0) 46 write cycle bank 0 active cl = 2 bl = 4 bank0 access = vih or vil bank 0 active bank 0 write bank 0 precharge tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih vih trcd tras trc trp twr /cs ck /ck cke /ras /cas /we ba a10 address dq (input) dm dqs (input) tck tch tcl tds tds tds tdh tdh tdh tdqsh tdqsl twpst tdqss
edk2516cbbh preliminary data sheet e0300e90 (ver. 9.0) 47 mode register set cycle t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 /ck ck cke /cs /ras /cas /we ba address dm dq (output) b valid code code trp precharge if needed mode register set bank 3 active bank 3 read r: b c: b vih bank 3 precharge tmrd high-z high-z cl = 3 bl = 4 = vih or vil dqs read/write cycle r:a c:a c:b r:b c:b'' b?? bank 0 active bank 3 active bank 0 read bank 3 read t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 cke /ras /cs dqs /cas /we address ck ba dq (output) dq (input) /ck bank 3 write twrd high-z vih trwd b read cycle cl = 3 bl = 4 =vih or vil dm a
edk2516cbbh preliminary data sheet e0300e90 (ver. 9.0) 48 auto refresh cycle precharge if needed auto refresh bank 0 active bank 0 read /ck ck cke /cs /cas /we ba address dm dq (output) dq (input) /ras cl = 3 bl = 4 = vih or vil vih trp a10=1 r: b c: b b high-z trfc dqs
edk2516cbbh preliminary data sheet e0300e90 (ver. 9.0) 49 self refresh cycle self refresh entry self refresh exit high-z /ck cke /cs /ras /cas /we ba address dm dq (output) dq (input) ck precharge if needed bank 0 active bank 0 read trp tsrex a10=1 r: b c: b dqs bl = 4 = vih or vil tis tih cke = low
edk2516cbbh preliminary data sheet e0300e90 (ver. 9.0) 50 deep power down entry cke /cs /ras /cas /we ba0 a10 address dm dq ba1 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t15 t16 t17 high-z precharge all banks command deep power down entry l ck /ck trp
edk2516cbbh preliminary data sheet e0300e90 (ver. 9.0) 51 deep power down exit cke /cs /ras /cas /we ba1 a10 address dm dq high-z tmrd tmrd address key address key 2 refresh cycles are necessary trfc trfc precharge all banks command is necessary deep power down exit command mode register set command is necessary extended mode register set command is necessary cbr (auto) refresh command is necessary activate command cbr (auto) refresh command is necessary ba0 clock cycle is necessary ck /ck trp 200 s vih vih
edk2516cbbh preliminary data sheet e0300e90 (ver. 9.0) 52 package drawing 60-ball fbga solder ball: lead free (sn-ag-cu) 60- 0.45 0.05 9.0 0.1 index area 1.6 13.0 0.1 0.1 s 0.2 s 1.20 max. 0.35 0.05 s b a index mark 1.3 6.4 0.8 2.9 0.8 0.4 7.2 abcdefghjk 13 279 8 unit: mm 0.15 sb 0.08 msa b eca-ts2-0088-01 0.15 sa
edk2516cbbh preliminary data sheet e0300e90 (ver. 9.0) 53 recommended soldering conditions please consult with our sales offices for soldering conditions of the edk2516cbbh. type of surface mount device edk2516cbbh: 60-ball fbga < lead free (sn-ag-cu) >
edk2516cbbh preliminary data sheet e0300e90 (ver. 9.0) 54 notes for cmos devices 1 precaution against esd for mos devices exposing the mos devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the mos devices operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. mos devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. mos devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor mos devices on it. 2 handling of unused input pins for cmos devices no connection for cmos devices input pins can be a cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. the unused pins must be handled in accordance with the related specifications. 3 status before initialization of mos devices power-on does not necessarily define initial status of mos devices. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the mos devices with reset function have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. mos devices are not initialized until the reset signal is received. reset operation must be executed immediately after power-on for mos devices having reset function. cme0107
edk2516cbbh preliminary data sheet e0300e90 (ver. 9.0) 55 mobile ram is a trademark of elpida memory, inc. m01e0107 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of elpida memory, inc. elpida memory, inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of elpida memory, inc. or third parties by or arising from the use of the products or information listed in this document. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of elpida memory, inc. or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. elpida memory, inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [product applications] elpida memory, inc. makes every attempt to ensure that its products are of high quality and reliability. however, users are instructed to contact elpida memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [product usage] design your application so that the product is used within the ranges and conditions guaranteed by elpida memory, inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. elpida memory, inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating elpida memory, inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the elpida memory, inc. product. [usage environment] this product is not designed to be resistant to electromagnetic waves or radiation. this product must be used in a non-condensing environment. if you export the products or technology described in this document that are controlled by the foreign exchange and foreign trade law of japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of japan. also, if you export products/technology controlled by u.s. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. if these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. the information in this document is subject to change without notice. before using this document, confirm that this is the late st version.

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